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EURASIP Journal on Applied Signal Processing has published
the following special issue online. Please visit the
journal's web site for links to abstracts and full-text
articles:


   Special Issue on
   Rapid Prototyping of DSP Systems


 o Editorial, Magdy Bayoumi, Shuvra S. Bhattacharyya,
   and Rudy Lauwereins


 o A Partitioning Methodology that Optimises the Area
   on Reconfigurable Real-Time Embedded Systems,
   Camel Tanougast, Yves Berviller, Serge Weber,
   and Philippe Brunet


 o Designing BEE: A Hardware Emulation Engine for Signal
   Processing in Low-Power Wireless Applications,
   Kimmo Kuusilinna, Chen Chang, M. Josephine Ammer,
   Brian C. Richards, and Robert W. Brodersen


 o Memory-Optimized Software Synthesis from Dataflow Program
   Graphs with Large Size Data Samples, Hyunok Oh
   and Soonhoi Ha


 o An FPGA Implementation of $(3,6)$-Regular Low-Density
   Parity-Check Code Decoder, Tong Zhang and Keshab K. Parhi


 o Rapid Prototyping of Field Programmable Gate Array-Based
   Discrete Cosine Transform Approximations, Trevor W. Fox
   and Laurence E. Turner


 o A Methodology for Rapid Prototyping Peak-Constrained
   Least-Squares Bit-Serial Finite Impulse Response Filters
   in FPGAs, Alex Carreira, Trevor W. Fox,
   and Laurence E. Turner


 o Logic Foundry: Rapid Prototyping for FPGA-Based DSP
   Systems, Gary Spivey, Shuvra S. Bhattacharyya,
   and Kazuo Nakajima


 o How Rapid is Rapid Prototyping? Analysis of ESPADON
   Programme Results, Bob K. Madahar, Ian D. Alston,
   Denis Aulagnier, Hans Schurer, Mark Thomas,
   and Brigitte Saget


 o Design and Implementation of Digital Linear Control
   Systems on Reconfigurable Hardware, Marcus Bednara,
   Klaus Danne, Markus Deppe, Oliver Oberschelp,
   Frank Slomka, and J�rgen Teich


 o A Rapid Prototyping Environment for Wireless
   Communication Embedded Systems, Bryan A. Jones
   and Joseph R. Cavallaro

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